Title :
A time optimal robust path-delay-fault self-testable adder
Author :
Becker, Bernd ; Drechsler, Rolf
Author_Institution :
Dept. of Comput. Sci., Johann Wolfgang Goethe-Univ., Frankfurt, Germany
Abstract :
A log(n)-time robust path-delay-fault (PDF) testable adder is presented. The adder is a modified version of a conditional carry adder (CCA). An optimal test set of size Θ(n2 ×log(n)) is constructed. The realization of a selftest for the adder is discussed; an algorithm of complexity O (n3) for the generation of a complete test set is used. A short hardware analysis of the CCA and its robust PDF-modification are presented
Keywords :
adders; computational complexity; delays; design for testability; fault location; logic testing; complexity; conditional carry adder; hardware analysis; optimal test set; time optimal robust path-delay-fault self-testable adder; Adders; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Frequency; Integrated circuit testing; Logic testing; Robustness; Very large scale integration;
Conference_Titel :
Design Automation Conference, 1992., EURO-VHDL '92, EURO-DAC '92. European
Conference_Location :
Hamburg
Print_ISBN :
0-8186-2780-8
DOI :
10.1109/EURDAC.1992.246216
