A scan cell architecture for inter-clock at-speed delay testing

At-speed delay testing is inevitable for improving the test quality of modern high-speed semiconductor chips. This paper presents a scan cell architecture for at-speed testing of delay faults in inter-clock logic. The technique utilizes commercially available ATPG tools for test pattern generation and internal PLL clocks for test pattern application. The hardware modification is contained within the scan cells and no additional global routing is required. Simulation results using three industrial designs demonstrate that the technique is effective in detecting delay faults in inter-clock logic.