• DocumentCode
    3374684
  • Title

    An optimal channel pin assignment with multiple intervals for building block layout

  • Author

    Koide, Tetsushi ; Wakabayashi, Shin´ichi ; Yoshida, Noriyoshi

  • Author_Institution
    Fac. of Eng., Hiroshima Univ., Japan
  • fYear
    1992
  • fDate
    7-10 Sep 1992
  • Firstpage
    348
  • Lastpage
    353
  • Abstract
    The authors present a linear time optimal algorithm to determine positions of the pins of nets on the top and the bottom sides of a channel, which is partitioned into several intervals. The pins are permutable within their associated intervals. The proposed algorithm is optimal in the sense that it can minimize both the density and the total wire length of the channel. Experimental results show that sufficient reduction of the channel density and the total wire length is, in fact, obtained by the use of the algorithm
  • Keywords
    VLSI; circuit layout CAD; VLSI circuits; building block layout; channel density; linear time optimal algorithm; multiple intervals; optimal channel pin assignment; total wire length; Algorithm design and analysis; Circuits; Computational modeling; Partitioning algorithms; Pins; Routing; Shape; Simulated annealing; Very large scale integration; Wire;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation Conference, 1992., EURO-VHDL '92, EURO-DAC '92. European
  • Conference_Location
    Hamburg
  • Print_ISBN
    0-8186-2780-8
  • Type

    conf

  • DOI
    10.1109/EURDAC.1992.246220
  • Filename
    246220