DocumentCode
3374700
Title
Exponent monitoring for low-cost concurrent error detection in FPU control logic
Author
Maniatakos, Michail ; Makris, Yiorgos ; Kudva, Prabhakar ; Fleischer, Bruce
Author_Institution
EE Dept., Yale Univ., New Haven, CT, USA
fYear
2011
fDate
1-5 May 2011
Firstpage
235
Lastpage
240
Abstract
We present a non-intrusive concurrent error detection (CED) method for protecting the control logic of a contemporary floating point unit (FPU). The proposed method is based on the observation that control logic errors lead to extensive datapath corruption and affect, with high probability, the exponent part of the IEEE 754 floating point representation. Thus, exponent monitoring can be utilized to detect errors in the control logic of the FPU. Predicting the exponent involves relatively simple operations, therefore our method incurs significantly lower overhead than the classical approach of duplicating the control logic of the FPU. Indeed, experimental results on the openSPARC T1 processor show that, as compared to control logic duplication, which incurs an area overhead of 17.9% of the FPU size, our method incurs an area overhead of only 5.8% yet still achieves detection of over 95% of transient errors in the FPU control logic. Moreover, the proposed method offers the ancillary benefit of also detecting 98.1% of datapath errors that affect the exponent, which cannot be detected via duplication of control logic. Finally, when combined with a classical residue code-based method for the fraction, our method leads to a complete CED solution for the entire FPU which provides a coverage of 94.4% of all errors at an area cost of 16.32% of the FPU size.
Keywords
floating point arithmetic; logic circuits; FPU control logic; IEEE 754 floating point representation; datapath corruption; exponent monitoring; floating point unit; low-cost concurrent error detection; nonintrusive concurrent error detection; openSPARC T1 processor; residue code-based method; Assembly; Hardware; Microprocessors; Monitoring; Pipelines; Registers; Transient analysis;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Test Symposium (VTS), 2011 IEEE 29th
Conference_Location
Dana Point, CA
ISSN
1093-0167
Print_ISBN
978-1-61284-657-6
Type
conf
DOI
10.1109/VTS.2011.5783727
Filename
5783727
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