Memory-based embedded digital ATE

This paper presents memory-based embedded digital ATE (Automatic Test Equipment) - a new logic BIST methodology that can deliver deterministic test stimuli and stores output responses on a chip. The proposed scheme consists of test data compression logic and a new on-chip SRAM structure, which is operated as a ROM when the logic BIST mode is on. The new BIST-oriented RAM (BRAM) implements ROM features in the BIST mode and incurs no performance penalty in the normal SRAM mode of operation. BRAM can be designed by inserting an additional word line in a row to a conventional SRAM bit-cell (no increase in bit-cell area). BRAM stores the compressed test vectors that can be transmitted to on-chip decompressors during test mode. BRAM also accepts compacted output responses. Experimental results show that BRAM performs stable and high-performance ROM operations in the BIST mode. Run-length coding can be incorporated into the proposed test data compression to reduce test data volume further. Test data volume and fault coverage on ISCAS89 benchmark show that the proposed test methodology can be used as a stand-alone BIST scheme while providing test quality of deterministic tests.