DocumentCode
3374841
Title
The impact of lossy line propagation on large die
Author
Davidson, Evan ; McCredie, Brad ; Vilkeiis, W.
Author_Institution
IBM Corp., Poughkeepsie, NY, USA
fYear
1995
fDate
2-4 Oct 1995
Firstpage
20
Abstract
Contrary to popular opinion, smaller feature sizes are not always faster when it comes to designing large custom CMOS die. This is due to the fact that at and below 0.5 micron ground rules, metal line cross-sections are becoming so small that lossy line propagation performance degraders are becoming significant. This knowledge was garnered by analyzing a real microprocessor design and comparing this data with a theoretical wiring model. However, the use of a multi-chip die (MCD) rather than an oversized die can result in a significant cost-performance advantage for a large complex system function such as a microprocessor
Keywords
CMOS digital integrated circuits; application specific integrated circuits; integrated circuit design; microprocessor chips; 0.5 micron; design; ground rules; large custom CMOS die; lossy line propagation; metal lines; microprocessor; multi-chip die; wiring model; CMOS process; Clocks; Degradation; Delay; Electronics packaging; Game theory; Microprocessors; Performance loss; Propagation losses; Wiring;
fLanguage
English
Publisher
ieee
Conference_Titel
Electrical Performance of Electronic Packaging, 1995
Conference_Location
Portland, OR
Print_ISBN
0-7803-3034-X
Type
conf
DOI
10.1109/EPEP.1995.524682
Filename
524682
Link To Document