A multilevel testability assistant for VLSI design

Author

Bombana, M. ; Buonanno, G. ; Cavalloro, P. ; Sciuto, D. ; Zaza, G.

Author_Institution

Italtel, Milano, Italy

fYear

1992

fDate

7-10 Sep 1992

Firstpage

258

Lastpage

263

Abstract

The possibility of applying techniques for VLSI testability analysis at abstract design levels will considerably help in reducing system design costs. A new approach to high-level testability analysis has been introduced at different design representation levels. A testability assistant has been defined to support the VLSI designer on testability and design for testability issues. The testability assistant is composed of a multilevel testability analyzer and a testability adviser. The authors describe the architecture of the high-level testability analyzer by defining its knowledge base and its basic modules

Keywords

VLSI; design for testability; integrated circuit testing; knowledge based systems; logic testing; VLSI design; VLSI testability analysis; abstract design levels; basic modules; design representation levels; knowledge base; logic testing; multilevel testability analyzer; multilevel testability assistant; system design costs; testability adviser; Analytical models; Circuit testing; Computational modeling; Costs; Logic testing; Performance evaluation; Power generation; System analysis and design; System testing; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 1992., EURO-VHDL '92, EURO-DAC '92. European

Conference_Location

Hamburg

Print_ISBN

0-8186-2780-8

Type

conf

DOI

10.1109/EURDAC.1992.246234

Filename

246234