Title :
Test and characterization of high-speed circuits
Author_Institution :
Broadcom, USA
Abstract :
Test, validation and characterization of high-speed circuits is a becoming a complex issue due to increase in circuit marginality, higher fallout, and more complex test solutions. The issue is compounded by the complex interactions between packaged components; interconnect design and customer board designs. This session will address the challenges in characterizing high-speed circuits including PLLs and SERDES. It describes test methodologies to overcome those challenges using industrial test cases.
Keywords :
high-speed integrated circuits; integrated circuit design; integrated circuit testing; phase locked loops; PLL; SERDES; customer board designs; high-speed circuits; industrial test; interconnect design; packaged components;
Conference_Titel :
VLSI Test Symposium (VTS), 2011 IEEE 29th
Conference_Location :
Dana Point, CA
Print_ISBN :
978-1-61284-657-6
DOI :
10.1109/VTS.2011.5783745
