Title :
A novel trench formation and planarization technique using positive etching and CMP for smart power ICs
Author :
Kim, Sang-Gi ; Kim, Jongdae ; Lee, Ju-Wook ; Koo, Jin-Gun ; Nam, ECee-Soo
Author_Institution :
Electron. & Telecommun. Res. Inst., Daejeon, South Korea
Abstract :
A new trench isolation technique has been demonstrated which can be used to make high voltage integrated circuits with trench isolation. The technique consists of positive etching using HBr and SiF4 chemistries with 45% He-O2 additives and global planarization after trench refill techniques using chemical-mechanical polishing (CMP). The novel technique provides better surface quality of 3.1 Å RMS roughness as measured by AFM, better CMP uniformity of less than 3%, and better leakage characteristics of less than 1 nA at 400 V
Keywords :
atomic force microscopy; isolation technology; leakage currents; polishing; power integrated circuits; sputter etching; surface chemistry; surface topography; 1 nA; 3.1 angstrom; 400 V; AFM; CMP; CMP uniformity; HBr etch chemistry; HBr-He-O2; He-O2 additives; SiF4 etch chemistry; SiF4-He-O2; chemical-mechanical polishing; global planarization; high voltage integrated circuits; leakage characteristics; positive etching; smart power ICs; surface quality; surface roughness; trench formation; trench isolation; trench isolation technique; trench planarization; trench refill techniques; Additives; Chemistry; Dry etching; Integrated circuit technology; Magnetic materials; Planarization; Power integrated circuits; Rough surfaces; Surface roughness; Voltage;
Conference_Titel :
Power Semiconductor Devices and ICs, 1998. ISPSD 98. Proceedings of the 10th International Symposium on
Conference_Location :
Kyoto
Print_ISBN :
0-7803-4752-8
DOI :
10.1109/ISPSD.1998.702718
