DocumentCode
3375424
Title
Area-Aware Optimizations for Resource Constrained Branch Predictors Exploited in Embedded Processors
Author
Salamat, Babak ; Baniasadi, Amirali ; Deris, Kaveh
Author_Institution
Sch. of Inf. & Comput. Sci., California Univ., Irvine, CA
fYear
2006
fDate
38899
Firstpage
50
Lastpage
55
Abstract
Modern embedded processors (e.g., Intel´s XScale) use small and simple branch predictors to improve performance. Such predictors impose little area and power overhead but may offer low accuracy. As a result, branch misprediction rate could be high. Such mispredictions result in longer program runtime and wasted activity. To address this inefficiency, we introduce two optimization techniques: first, we introduce an adaptive and low-complexity branch prediction technique. Our branch predictor removes up to a maximum of 50% of the branch mispredictions of a bimodal predictor. This results in improving performance by up to 16%. Second, we present front-end gating techniques and reduce wasted activity up to a maximum of 32%
Keywords
embedded systems; instruction sets; microprocessor chips; optimising compilers; power aware computing; area-aware optimizations; embedded processors; front-end gating techniques; low-complexity branch prediction technique; resource constrained branch predictors; Constraint optimization; Costs; Counting circuits; Embedded computing; Hardware; History; Performance evaluation; Pipelines; Runtime; Switches;
fLanguage
English
Publisher
ieee
Conference_Titel
Embedded Computer Systems: Architectures, Modeling and Simulation, 2006. IC-SAMOS 2006. International Conference on
Conference_Location
Samos
Print_ISBN
1-4244-0155-0
Type
conf
DOI
10.1109/ICSAMOS.2006.300808
Filename
4084749
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