Combined topological and functionality based delay estimation using at layout-driven approach for high level applications

The problem of accurate delay estimation of cell-based designs, prior to any physical design tasks, is discussed. For this purpose, accurate wire-length estimates are required, since wire delays contribute significantly to the overall delay. A new technique is presented for wire-length estimation based on a combination of analytical and constructive approaches. Given these wire-length estimates and the cell delays, it is possible to provide worst case delay paths in the design based on the circuit topology. The technique is extended to consider false paths, which provides a more accurate functionality based estimate which takes into account the estimated layout information. The technique is validated using standard MCNC benchmarks. Results indicate a 7% or better accuracy in the worst case delay predictions for designs with up to 1800 cells