A thermal-driven force-directed floorplanning algorithm for 3D ICs

The three-dimensional (3D) integration circuit is a new technology with higher integration density. To solve the critical thermal issue in 3D layout, we propose a thermal-driven force-directed floorplanning algorithm. Based on the characteristic of the different stages of floorplanning, this algorithm applies different methods to calculate the thermal distribution to reach a tradeoff between time efficiency and accuracy. And a new effective strategy of the layer assignment is used in which we consider the area, the overlaps and the power densities simultaneously. Experimental results show that, compared with the recent thermal-driven force-directed 3D floorplanner, it averagely decreases the temperature by 8% and runtime by 10.7% while only increases the area and wirelength by 3% at most.