Automatic stress effects computation based on a layout generation tool for analog IC

This paper studies the matching and the stress effect problems that appear in deep submicron CMOS technologies. These effects significantly affect the electrical behavior of CMOS transistors. We propose a method to compute stress effect parameters resulting from different layout styles such as interdigitated and symmetrical styles. We apply this method to a transistor device and a differential pair device. We also quantify the errors due to transistor folding and stress effects in 65 nm CMOS technology for different device layouts. The results show the effectiveness of the proposed method.