DocumentCode
3375596
Title
Communication based logic partitioning
Author
Beardslee, Mark ; Lin, Bill ; Sangiovanni-Vincentilli, A.
Author_Institution
California Univ., Berkeley, CA, USA
fYear
1992
fDate
7-10 Sep 1992
Firstpage
32
Lastpage
37
Abstract
The problem of partitioning, or decomposing a combinational logic specification is addressed. This method operates on the logic specification before the synthesis and mapping steps have been performed. This allows good circuit decomposition and the logic as needed. The main goal of the algorithm is to minimize the number of pins needed to implement the resulting partitions. This is accomplished by adding logic to reduce the number of pins, and by minimizing the number of pins required for inter-partition communication by encoding the signals that flow between partitions. Algorithms are implemented by the use of binary decision diagrams
Keywords
circuit layout CAD; combinatorial circuits; logic CAD; binary decision diagrams; circuit decomposition; combinational logic specification; communication based logic partitioning; encoding; inter-partition communication; logic specification; mapping; Circuit synthesis; Costs; Hardware; Latches; Logic circuits; Manufacturing; Packaging; Partitioning algorithms; Pins; Signal design;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 1992., EURO-VHDL '92, EURO-DAC '92. European
Conference_Location
Hamburg
Print_ISBN
0-8186-2780-8
Type
conf
DOI
10.1109/EURDAC.1992.246268
Filename
246268
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