DocumentCode :
3375670
Title :
Power-aware test generation with guaranteed launch safety for at-speed scan testing
Author :
Wen, X. ; Enokimoto, K. ; Miyase, K. ; Yamato, Y. ; Kochte, M.A. ; Kajihara, S. ; Girard, P. ; Tehranipoor, M.
Author_Institution :
Kyushu Inst. of Technol., Iizuka, Japan
fYear :
2011
fDate :
1-5 May 2011
Firstpage :
166
Lastpage :
171
Abstract :
At-speed scan testing may suffer from severe yield loss due to the launch safety problem, where test responses are invalidated by excessive launch switching activity (LSA) caused by test stimulus launching in the at-speed test cycle. However, previous low-power test generation techniques can only reduce LSA to some extent but cannot guarantee launch safety. This paper proposes a novel & practical power-aware test generation flow, featuring guaranteed launch safety. The basic idea is to enhance ATPG with a unique two-phase (rescue & mask) scheme by targeting at the real cause of the launch safety problem, i.e., the excessive LSA in the neighboring areas (namely impact areas) around long paths sensitized by a test vector. The rescue phase is to reduce excessive LSA in impact areas in a focused manner, and the mask phase is to exclude from use in fault detection the uncertain test response at the endpoint of any long sensitized path that still has excessive LSA in its impact area even after the rescue phase is executed. This scheme is the first of its kind for achieving guaranteed launch safety with minimal impact on test quality and test costs, which is the ultimate goal of power-aware at-speed scan test generation.
Keywords :
automatic test pattern generation; fault diagnosis; logic testing; ATPG; at-speed scan testing; fault detection; guaranteed launch safety; launch switching activity; low-power test generation; power-aware test generation; rescue & mask scheme; Automatic test pattern generation; Circuit faults; Compaction; Fault detection; Lead; Safety; at-speed scan testing; launch safety; power supply noise; test generation; test power;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Test Symposium (VTS), 2011 IEEE 29th
Conference_Location :
Dana Point, CA
ISSN :
1093-0167
Print_ISBN :
978-1-61284-657-6
Type :
conf
DOI :
10.1109/VTS.2011.5783778
Filename :
5783778
Link To Document :
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