DocumentCode
3375791
Title
An analytical method for estimating SET propagation
Author
Gangadhar, Sreenivas ; Tragoudas, Spyros
Author_Institution
Dept. of Electr. & Comput. Eng., Southern Illinois Univ. Carbondale, Carbondale, IL, USA
fYear
2011
fDate
1-5 May 2011
Firstpage
197
Lastpage
202
Abstract
In sub-micron technology, a small inaccuracy in computing the probability of occurrence of a soft error results into an unacceptable chip failure rate. A method to estimate the probability of SET propagation to the output gate at any time instant within the latching window is proposed. Its accuracy is evaluated using Monte Carlo simulations.
Keywords
Monte Carlo methods; flip-flops; logic gates; probability; Monte Carlo simulations; SET propagation; latching window; output gate; probability; soft error; submicron technology; unacceptable chip failure rate; Attenuation; Boolean functions; Delay; Equations; Integrated circuit modeling; Logic gates; Monte Carlo methods;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Test Symposium (VTS), 2011 IEEE 29th
Conference_Location
Dana Point, CA
ISSN
1093-0167
Print_ISBN
978-1-61284-657-6
Type
conf
DOI
10.1109/VTS.2011.5783783
Filename
5783783
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