Experiments on the synthesis and testability of non-scan finite state machines

Synthesis of testable sequential circuits has been proposed as an alternative to scan design methodologies. A number of synthesis procedures have been proposed to eliminate some or all combinational redundancies (CRs) and sequential redundancies (SRs). The latter are in principle the harder to detect and remove. Experiments on single-stuck fault testability of finite state machines (FSMs) implemented with different synthesis tools have been carried out. The benchmark suite included MCNC and ISCAS circuits as well as industrial examples from Siemens. The experiments showed that SRs requiring intensive CPU time and memory space to be detected occur very seldom. Single-stuck fault coverage obtained by state-of-the-art synthesis and test generation algorithms is >99% for non-scan FSMs with up to about 100 states