Design space exploration and performance evaluation at Electronic System Level for NoC-based MPSoC

System-on-Chip (SoC) has become a common design technique in the integrated circuits industry as it offers many advantages in terms of cost and performance efficiency. SoCs are increasingly complex and heterogeneous systems that are highly integrated comprising processors, caches, hardware accelerators, memories, peripherals and interconnects. Modern SoCs deploy not only simple buses but also crossbars and Networks-on-Chip (NoC) to connect dozens or even hundreds of modules. However, it is difficult to evaluate the performance of these interconnects because of their complexity. This is a potential design risk. In order to address this challenge, early design space exploration is required to find appropriate system architectures out of many candidate architectures. An appropriate interconnect architecture is a fundamental outcome of these evaluations since its latency and throughput characteristics affect the performance of all attached modules in the SoC. In this paper we show how to perform early design space exploration using our Electronic System Level (ESL) performance evaluation framework SystemQ. We use a heterogeneous MultiProcessor SoC that features a complex NoC as a central interconnect. Based on this example we show the importance of proper abstraction in order to keep simulation efforts manageable.