• DocumentCode
    3375861
  • Title

    Coverage closure in SoC verification: Are we chasing a mirage?

  • Author

    Vasudevan, Shobha

  • Author_Institution
    Univ. of Illinois at Urbana, Champaign, IL, USA
  • fYear
    2011
  • fDate
    1-5 May 2011
  • Firstpage
    211
  • Lastpage
    211
  • Abstract
    With over 78% of designs being heterogeneous integrations of diverse components, SoCs are ubiquitous. This integration, though, brings with it the malaise of challenges in verification and validation. SoC verification has a number of unique challenges beyond traditional ASIC type of designs. The typical SoC flow consists of the following development phases: System Design, Software Design, HW/SW Integration, SoC HW Integration and HW IP design.
  • Keywords
    hardware-software codesign; system-on-chip; ASIC; HW IP design; HW/SW integration; SoC HW integration; SoC flow; SoC verification; software design; system design; IP networks; Industries; Silicon; System-on-a-chip; Virtual prototyping; Watches;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Test Symposium (VTS), 2011 IEEE 29th
  • Conference_Location
    Dana Point, CA
  • ISSN
    1093-0167
  • Print_ISBN
    978-1-61284-657-6
  • Type

    conf

  • DOI
    10.1109/VTS.2011.5783786
  • Filename
    5783786
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3375861