DocumentCode
3375887
Title
Cache designs with partial address matching
Author
Liu, Lishing
Author_Institution
IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
fYear
1994
fDate
30 Nov.-2 Dec. 1994
Firstpage
128
Lastpage
136
Abstract
One critical aspect in designing set-associative cache at high clock rate is deriving timely results from directory lookup. In this paper we investigate the possibility of accurately approximating the results of conventional directory search with faster matches of few partial address bits. Such fast and accurate approximations may be utilized to optimize cache access timing, particularly in a customized design environment. Through analytic and simulation studies we examine the trade-offs of various design choices. We also discuss few other applications of partial address matching to computer designs.
Keywords
cache storage; file organisation; storage management; cache designs; customized design environment; directory lookup; directory search; high clock rate; partial address matching; simulation studies; Application software; Circuits; Clocks; Computational modeling; Costs; Decoding; Design optimization; Energy consumption; System performance; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Microarchitecture, 1994. MICRO-27. Proceedings of the 27th Annual International Symposium on
ISSN
1072-4451
Print_ISBN
0-89791-707-3
Type
conf
DOI
10.1109/MICRO.1994.717450
Filename
717450
Link To Document