N × 16 cellular test chips for low-pass filtering large images

In this paper, measurement results of a test chip realizing low-pass filtering parallel processor are given and some of the observed problems are discussed. The chip was designed to test the implementation of a network processor where the size of the network is smaller than the actual image size. In this processor it is possible to write in, calculate the output and read out the results simultaneously. In this way savings can be achieved in silicon size, power consumption and processing time. Measurement results indicate that the system is functional in principle and is capable of processing thousands of images in a second. But, also several problems were found. A new design is introduced where the problems found in the first design are taken into account and a larger grid size chip was implemented. The goal of the new chip is to investigate the problems in designing this kind of a system in a larger scale. Some preliminary measurement results were also available at the time of writing and they were included in the article.