8×8-Bit multiplier designed with a new wave-pipelining scheme

In this paper, a new wave-pipelining scheme is proposed. In classical wave-pipelining scheme, the data waves propagate on the circuit and the propagating waves are sampled simultaneously when they reach to a synchronization stage. In this new wave-pipelining scheme, only the components of the wave whose delay-difference values reach to a critical value are sampled. Other components, which are not sampled, are aligned with the sampled ones by using active delay elements. This wave-pipelining scheme significantly decreases the number of flip-flops which are used to synchronize the propagating waves. For demonstrating the effectiveness of the new wave-pipelining scheme, an 8×8-bit carry save multiplier is implemented using 0.35um standard CMOS process. Simulation results show that, the multiplier can operate at a speed of 2GHz, by using only 55 flip-flops. Comparing with the mesochronous pipelining scheme, the number of the flip-flops is decreased by 47%.