Facilitating superscalar processing via a combined static/dynamic register renaming scheme

A superscalar implementation of a conventional instruction set architecture (ISA) requires N(N-1) comparators to determine dependencies between the N instructions issuing concurrently and 2N register file read ports to handle the 2 operands that each instruction can potentially source. On the other hand, if the compiler is allowed to specify part of the renaming tag, we show that we can eliminate the comparators needed to detect data dependencies between instructions issuing concurrently, and we can reduce the number of read ports from 16 to about 7 without losing performance. Finally, we show that this approach more efficiently implements predicated execution than can be done with a conventional ISA on a machine that renames registers.