Hardware complexity of a correlation based background DAC error estimation technique for sigma-delta ADCs

This paper presents different alternatives for a hardware realization of a previously proposed correlation based background error estimation and correction technique. The technique is used to linearize the unit elements in the feedback DAC of a ΔΣ analog-to-digital converter (ΔΣ ADC). General system simplifications to reduce the necessary hardware are presented and verified by simulations. The hardware needed to realize key parts of the method-with the simplifications included-is compared between the different implementation alternatives. The hardware comparison is done for gate level implementations of an exemplary modulator, which is combined with the background estimation and correction system. Finally, the most suitable structure for an implementation is identified.