A numerical design approach for high speed, differential, resistor-loaded, CMOS amplifiers

Author

Crain, Ethan ; Perrott, Michael

Author_Institution

Microsystems Technol. Lab., MIT, Cambridge, MA, USA

Volume

5

fYear

2004

fDate

23-26 May 2004

Abstract

A simple numerical procedure is introduced to allow straight-forward design of high speed, resistor loaded, differential amplifiers in modern CMOS processes whose device characteristics dramatically depart from traditional square law characteristics. The analytical form of the procedure allows for an intuitive perspective of the varying gain-bandwidth product for such amplifiers. Calculations based on the method are compared to Hspice simulated results based on a 0.18 μm CMOS process. Its application to the design of high speed, source-coupled logic (SCL) gates and latches are also discussed.

Keywords

CMOS analogue integrated circuits; analogue integrated circuits; differential amplifiers; high-speed integrated circuits; integrated circuit design; logic gates; resistors; 0.18 micron; Hspice simulation; amplifier design; differential CMOS amplifiers; gain-bandwidth product; high speed CMOS amplifiers; high speed applications; latches; numerical design; resistor loaded CMOS amplifiers; source-coupled logic gates; square law characteristics; Bandwidth; CMOS process; CMOS technology; Capacitance; Circuit simulation; Differential amplifiers; Latches; Power amplifiers; Resistors; SPICE;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2004. ISCAS '04. Proceedings of the 2004 International Symposium on

Print_ISBN

0-7803-8251-X

Type

conf

DOI

10.1109/ISCAS.2004.1329698

Filename

1329698