DocumentCode
3376541
Title
Cross-layer error resilience for robust systems
Author
Leem, Larkhoon ; Cho, Hyungmin ; Lee, Hsiao-Heng ; Kim, Young Moon ; Li, Yanjing ; Mitra, Subhasish
Author_Institution
Dept. of Electr. Eng., Stanford Univ., Stanford, CA, USA
fYear
2010
fDate
7-11 Nov. 2010
Firstpage
177
Lastpage
180
Abstract
A large class of robust electronic systems of the future must be designed to perform correctly despite hardware failures. In contrast, today´s mainstream systems typically assume error-free hardware. Classical fault-tolerant computing techniques are too expensive for this purpose. This paper presents an overview of new techniques that can enable a sea change in the design of cost-effective robust systems. These techniques utilize globally-optimized cross-layer approaches, i.e., across device, circuit, architecture, runtime, and application layers, to overcome hardware failures.
Keywords
failure analysis; integrated circuit reliability; cost-effective robust systems; cross-layer error resilience; error-free hardware; robust electronic systems; Built-in self-test; Design automation; Hardware; Logic gates; Resilience; Robustness; CASP; ERSA; LEAP; circuit failure prediction; diagnostics; error resilient system architecture; on-line self-test; reliability; robust system design; soft error;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer-Aided Design (ICCAD), 2010 IEEE/ACM International Conference on
Conference_Location
San Jose, CA
ISSN
1092-3152
Print_ISBN
978-1-4244-8193-4
Type
conf
DOI
10.1109/ICCAD.2010.5654129
Filename
5654129
Link To Document