A high resolution metastability-independent two-step gated ring oscillator TDC with enhanced noise shaping

Author

Chung, Sang-Hye ; Hwang, Kyu-Dong ; Lee, Won-Young ; Kim, Lee-Sup

Author_Institution

Dept. of Electr. Eng., KAIST, Daejeon, South Korea

fYear

2010

fDate

May 30 2010-June 2 2010

Firstpage

1300

Lastpage

1303

Abstract

This paper presents a high resolution two-step gated-ring oscillator (TSGRO) time-to-digital converter (TDC) in an all digital phase-locked loop (ADPLL). TSGRO-TDC consists of a coarse step and a fine step gated-ring oscillator (GRO) TDC to achieve a high resolution. An edge aligner is used in the fine step GRO-TDC to enhance a first-order noise shaping property. A meta-stability free selection logic (MSFSL) is proposed in this paper which achieves low power and small area. In 0.13μm CMOS process, TSGRO-TDC has a 3ps raw resolution and first-order noise shaping.

Keywords

CMOS integrated circuits; circuit noise; circuit stability; digital phase locked loops; oscillators; CMOS process; all digital phase-locked loop; edge aligner; first-order noise shaping; high resolution metastability-independent two-step gated ring oscillator TDC; meta-stability free selection logic; size 0.13 mum; time-to-digital converter; CMOS process; Delay; Frequency synthesizers; Low pass filters; Metastasis; Noise figure; Noise shaping; Phase locked loops; Quantization; Ring oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on

Conference_Location

Paris

Print_ISBN

978-1-4244-5308-5

Electronic_ISBN

978-1-4244-5309-2

Type

conf

DOI

10.1109/ISCAS.2010.5537261

Filename

5537261