Title :
System-level impact of chip-level failure mechanisms and screens
Author_Institution :
IBM Res., Austin Res. Lab., Austin, TX, USA
Abstract :
This paper provides an overview of chip-level failure mechanisms and test screens. Emphasis is placed on detectability of defect mechanisms by chip-level test, trends that affect failure mechanisms and screens, and resulting implications for system-level yield and reliability.
Keywords :
failure analysis; integrated circuit reliability; integrated circuit testing; integrated circuit yield; chip-level failure mechanisms; chip-level test; defect mechanisms; reliability; system-level impact; system-level yield; test screens; Circuit faults; Failure analysis; Integrated circuit modeling; Reliability; Resistance; Systematics;
Conference_Titel :
Computer-Aided Design (ICCAD), 2010 IEEE/ACM International Conference on
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4244-8193-4
DOI :
10.1109/ICCAD.2010.5654135
