Non Overlapping Clock (NOC) generator for low frequency switched capacitor circuits

Switched capacitor techniques are very popular for implementation of Mixed Signal blocks in CMOS VLSI. Non-Overlapping Clock (NOC) generator is one of the key blocks in the implementation of switched capacitor circuits. Standard NOC generator circuits available in the literature uses delay circuits realized using simple inverters connected in a chain. For moderate frequencies, the number of inverters required for a reasonable non-overlapping period is nominal; however, for low frequency applications such as bio-medical signal processing, the number could be quite large. This affects the area and power budget of the design. In this work it is proposed to use inverters in inverted form to realize significant delay with less number of transistors. Simulation results suggest that the proposed circuit will be area and power efficient as compared to the conventional NOC circuits.