DocumentCode
3377331
Title
A self-evolving design methodology for power efficient multi-core systems
Author
Sun, Jin ; Rui Zheng ; Velamala, Jyothi ; Yu Cao ; Lysecky, Roman ; Shankar, Karthik ; Roveda, Janet
Author_Institution
Dept. of Electr. & Comput. Eng., Univ. of Arizona, Tucson, AZ, USA
fYear
2010
fDate
7-11 Nov. 2010
Firstpage
264
Lastpage
268
Abstract
This paper introduces a new methodology that characterizes aging-duty cycle and aging-supply voltage relationships that are applicable to minimizing power consumption and task execution time to achieve low Bit-Energy-Ratio (BER). In contrast to the traditional workload balancing scheme where cores are regarded as homogeneous, we proposed a new task scheduler that ranks cores according to their various competitiveness evaluated based upon their reliability, temperature and timing requirements. Consequently, the new approach combines internal characteristics (aging-duty cycle and aging-supply voltage curves) into an integrated framework to achieve system performance improvement or graceful degradation with high reliability and low power. Experimental results show that the proposed method has achieved 18% power reduction with about 4% performance degradation (in terms of accomplished workload) compared with traditional workload balancing methods.
Keywords
integrated circuit reliability; low-power electronics; monolithic integrated circuits; semiconductor device reliability; aging-duty cycle; aging-supply voltage; bit-energy-ratio; power consumption; power efficient multicore systems; self-evolving design methodology; Aging; Degradation; Error analysis; Power demand; Reliability; Temperature sensors; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer-Aided Design (ICCAD), 2010 IEEE/ACM International Conference on
Conference_Location
San Jose, CA
ISSN
1092-3152
Print_ISBN
978-1-4244-8193-4
Type
conf
DOI
10.1109/ICCAD.2010.5654175
Filename
5654175
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