On-the-fly runtime adaptation for efficient execution of parallel multi-algorithm circuit simulation

The past several years have witnessed a significant interest in developing parallel CAD algorithms and implementations that exploit various multi-core and distributed computing hardware. In addition to fundamental parallel algorithm design, the ability in modeling parallel performance and facilitating runtime optimization is indispensable for achieving good efficiency for complex parallel CAD applications. Under the context of a recently developed hierarchical multi-algorithm parallel circuit simulation (HMAPS) framework, we demonstrate a runtime optimization approach that allows for automatic on-the-fly reconfiguration of the parallel simulation code. We show how the runtime information, collected as parallel simulation proceeds, can be combined with static parallel performance models to enable dynamic adaptation of parallel simulation execution for improved performance and robustness. Our results have shown that the proposed approach not only finds the near-optimal code configuration over a large configuration space, it also outperforms multi-algorithm circuit simulation assisted only with static pre-runtime parallel performance modeling.