Title :
Real-time multi-view rendering architecture for autostereoscopic displays
Author :
Chen, Hsin-Jung ; Lo, Feng-Hsiang ; Jan, Fu-Chiang ; Wu, Sheng-Dong
Author_Institution :
Electron. & Optoelectron. Res. Labs., Ind. Technol. Res. Inst., Hsinchu, Taiwan
fDate :
May 30 2010-June 2 2010
Abstract :
Three-dimensional television (3D-TV) has attracted significant attention because of 3D immersive feeling for advanced TV development. Multi-view rendering by depth image based rendering (DIBR) and interlacing are the key technologies to realize 3D-TV system from content to display. In this paper, a new multi-view rendering hardware architecture consisting of hybrid parallel DBIR and pipeline interlacing are proposed to improve the performance. Experimental results show that the proposed architecture can achieve 60 frames per second for processing full HD (1920×1080) video in real-time processing system. Only 3% logic elements of ALTERA Cyclone III FPGA are used.
Keywords :
field programmable gate arrays; pipeline processing; rendering (computer graphics); television displays; three-dimensional displays; 3D TV; ALTERA Cyclone III FPGA; autostereoscopic displays; depth image based rendering; pipeline interlacing; real time multiview rendering architecture; real time processing system; three dimensional television; Cyclones; Displays; HDTV; Hardware; High definition video; Logic; Pipelines; Real time systems; Rendering (computer graphics); Three dimensional TV;
Conference_Titel :
Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on
Conference_Location :
Paris
Print_ISBN :
978-1-4244-5308-5
Electronic_ISBN :
978-1-4244-5309-2
DOI :
10.1109/ISCAS.2010.5537312
