Capacitor scaling for low-power design of cyclic analog-to-digital converters

In this paper, in order to reduce the power consumption of a cyclic ADC, for different cycles in digitizing an analog input sample, the values of the capacitors are scaled down. The power consumption of the operational amplifier is adaptively reduced as well. In order to demonstrate the effectiveness of the proposed technique, a 1.8V 12-bit 104kS/s ADC has been designed in a 0.18μm CMOS technology using the modified structure and compared with conventional implementation. HSpice simulations show that applying the technique has reduced the power consumption of the ADC with a factor of more than 2.1.