Title :
Optimized test cost using fault probabilities
Author_Institution :
Inst. of Comput. Design & Fault Tolerance, Karlsruhe Univ., Germany
Abstract :
The relation of quality and cost is an important measure for the efficiency of IC fabrication. In this paper, a method for the determination of product quality based on fault probabilities is introduced. An approach is presented for the calculation of fault probabilities using the idea of critical area. An algorithm for test cost optimization whilst a specified product quality is attained is proposed. Experimental results are discussed
Keywords :
economics; integrated circuit testing; optimisation; probability; production testing; quality control; IC fabrication; VLSI; critical area; fault probabilities; quality; test cost optimisation; test cost optimization; Circuit faults; Circuit testing; Cost function; Fabrication; Fault detection; Fault tolerance; Integrated circuit manufacture; Integrated circuit testing; Minimization; Probability;
Conference_Titel :
European Test Conference, 1993. Proceedings of ETC 93., Third
Conference_Location :
Rotterdam
Print_ISBN :
0-8186-3360-3
DOI :
10.1109/ETC.1993.246518
