Title :
Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078)
Abstract :
The following topics were dealt with: embedded system design; verification of sequential circuits; architectural issues in low power design; design reuse repository and IP architecture; high level verification; system-level power optimization; reconfigurability; embedded core test approaches; combinational verification; gate level power estimation and optimization; Virtual Socket Interface Alliance; fault diagnosis techniques for analogue circuits; resource sharing in architectural synthesis; mixed signal characterization and test; system design methodologies; high level test synthesis; analogue circuit sizing and synthesis; high-level system simulation; VHDL-AMS and HDL interoperability; transistor level test; hardware synthesis from C/C++ models; chip package co-design; scaling towards nanometer technologies; functional verification; bit-level logic simulation; partial and boundary scan test; logic synthesis; defect modelling; physical design issues; reliability and symmetry; retiming; interconnects modelling; virtual components; RAM BIST; sequential circuit test generation
Keywords :
circuit simulation; circuit testing; electronic design automation; high level synthesis; logic CAD; logic simulation; logic testing; HDL interoperability; IP architecture; RAM BIST; VHDL-AMS; Virtual Socket Interface Alliance; analogue circuits; architectural issues; architectural synthesis; bit-level logic simulation; boundary scan test; chip package co-design; combinational verification; defect modelling; design reuse repository; embedded core test approaches; embedded system design; fault diagnosis techniques; functional verification; gate level power estimation; hardware synthesis from C/C++ models; high level test synthesis; high level verification; high-level system simulation; interconnects modelling; logic synthesis; low power design; mixed signal characterization; mixed signal test; nanometer technologies; partial scan test; physical design issues; reconfigurability; reliability; resource sharing; retiming; sequential circuit test generation; sequential circuits verification; symmetry; system design methodologies; system-level power optimization; transistor level test; virtual components; Automatic testing; Circuit synthesis; Circuit testing; Design automation; Europe; Logic testing; Sequential analysis; Sequential circuits; Signal design; System testing;
Conference_Titel :
Design, Automation and Test in Europe Conference and Exhibition 1999. Proceedings
Conference_Location :
Munich, Germany
Print_ISBN :
0-7695-0078-1
DOI :
10.1109/DATE.1999.761086
