• DocumentCode
    3377861
  • Title

    Optimum array-like structures for high-speed arithmetic

  • Author

    Agrawal, Dharma P.

  • Author_Institution
    Mini and Microcomputer Laboratory, Swiss Federal Institute of Technology, Ch. de Bellerive 16, CH-1007 Lausanne Switzerland
  • fYear
    1975
  • fDate
    19-20 Nov. 1975
  • Firstpage
    208
  • Lastpage
    219
  • Abstract
    Array-like structures for high-speed multiplication, division, square and square-root operations have been described in this paper. In these designs the division and square-rooting time have been made to approach to that of multiplication operation. These structures are optimum from speed and versatility point of view. Most of the cellular arrays described in the literature are adequately slow. The time delay is particularly significant in the division and square-rooting operations due to the ripple effect of the carries. Though the carry-save technique has been widely utilized for multiplication operation, it has been only recently employed by Cappa et. al. in the design of a non-restoring divider array. This requires sign-bit detection that makes the array non-uniform. Such an array has been named as an array-like structure. The carry-save method has been extended here for restoring division operation. Due to sign-detection and overflow correction requirements, the restoring method is slightly complex. But the main advantage of such restoring array is in its simple extension for multiplication operation. The array for the two operations, when pipelined, will have more computing power than all other multiplier-divider arrays. Suggestions have also been included for further speed improvement. The technique applied for division operation is as well applicable for the square-rooting and an array-like structure for square-square-rooting operations has also been given. For performing any one of the four operations, the only manipulation to be done is to combine the two arrays; one for multiplication-division and another for square-square-rooting. Possible methods of combining the two arrays have been indicated and their relative advantages and disadvantages have been mentioned. Finally, a generalized pipeline array-like structure with complete internal details and for 4-bit operation, has been shown. Due consideration has also been given to the possibility of large-sca- e-integration of different arrays presented in this paper.
  • Keywords
    Adders; Array signal processing; Delay; Delay effects; Logic arrays; Logic gates; Transistors;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer Arithmetic (ARITH), 1975 IEEE 3rd Symposium on
  • Conference_Location
    Dallas, TX, USA
  • Type

    conf

  • DOI
    10.1109/ARITH.1975.6156968
  • Filename
    6156968