DocumentCode
3378050
Title
Concurrent error detection of CMOS digital and analog faults
Author
Shieh, Yeong-Ruey ; Wu, Cheng-Wen
Author_Institution
Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
fYear
1993
fDate
19-22 Apr 1993
Firstpage
74
Lastpage
81
Abstract
The authors present a novel approach to designing TSC (totally self-checking) CMOS circuits, considering transistor stuck-on faults. Their approach is delineated by a design-for-testability (DFT) technique, which requires a very small constant number of extra transistors, coupled with a simple clocking scheme, to detect the stuck-on faults concurrently. The DFT circuitry can defect the faults in the functional circuit and it can detect or tolerate the faults in itself
Keywords
CMOS integrated circuits; VLSI; built-in self test; design for testability; fault location; integrated logic circuits; logic testing; mixed analogue-digital integrated circuits; CMOS; analog faults; design-for-testability; functional circuit; transistor stuck-on faults; CMOS technology; Circuit faults; Circuit testing; Clocks; Degradation; Electrical fault detection; Fault detection; Monitoring; Semiconductor device modeling; Switching circuits;
fLanguage
English
Publisher
ieee
Conference_Titel
European Test Conference, 1993. Proceedings of ETC 93., Third
Conference_Location
Rotterdam
Print_ISBN
0-8186-3360-3
Type
conf
DOI
10.1109/ETC.1993.246531
Filename
246531
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