Si-MOSFET scaling down to deep-sub-0.1-micron range and future of silicon LSI

Author

Iwai, Hiroshi ; Momose, Hisayo Sasaki ; Katsumata, Yasuhiro

Author_Institution

Res. & Dev. Center, Toshiba Corp., Kawasaki, Japan

fYear

1995

fDate

31 May-2 Jun 1995

Firstpage

262

Lastpage

267

Abstract

The tremendous progress made with silicon LSIs over the past 25 years has been driven by the miniaturization of MOSFETs. Down-sizing MOSFETs below the 0.1 micron range, however, is proving technologically very difficult due to certain physical limitations. In this paper, we will demonstrate certain ways in which MOSFETs can be taken down to the deep-sub-0.1 micron regime, and also give our views on future LSIs using these MOSFETs

Keywords

MOSFET; large scale integration; semiconductor technology; silicon; technological forecasting; 0.1 micron; Si; Si-MOSFET scaling; deep-sub-0.1-micron range; down-sizing; miniaturization; silicon LSI; Electrodes; Electrons; Frequency; Laboratories; Large scale integration; MOSFETs; Microprocessors; Silicon; Switches; Ultra large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, Systems, and Applications, 1995. Proceedings of Technical Papers. 1995 International Symposium on

Conference_Location

Taipei

ISSN

1524-766X

Print_ISBN

0-7803-2773-X

Type

conf

DOI

10.1109/VTSA.1995.524700

Filename

524700

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3378110