Design of an arithmetic element for serial processing in an iterative structure

This paper describes the arithmetic and logic design of the digit processing logic of an arithmetic element. The arithmetic element is used in an iterative structure and arithmetic processing takes place serially on a digit by digit basis with the most significant digit first. Starting from the arithmetic specification of the digit processing logic, the arithmetic design (namely, the choice of number system, number representation and the digit algorithm) is developed. Algebraic and logic designs of the logic necessary to execute the digit algorithm and its implication for LSI implementation are discussed.