A framework for test quality assessment

This paper describes a novel framework for estimating the quality level of tests for digital circuits, using realistic fault models which represent faults that are likely to occur. The framework contains test pattern generation and fault simulation programs, automated logic synthesis and silicon compilation programs, and an inductive fault analysis (IFA) program. The framework is used to produce experimental results concerning the detection of realistic bridging faults using single stuck-at test sets. The results show that compact stuck-at test sets, generated using state-of-the-art dynamic compaction techniques, barely decrease the fault coverage of bridging faults, as compared with uncompacted test sets. In addition the paper shows that logic synthesis can be used to increase the realistic bridging fault coverage