DocumentCode :
3378229
Title :
Test pattern generation for multiple stuck-at faults
Author :
Karkouri, Younes ; Aboulhamid, El Mostapha ; Cerny, Eduard
Author_Institution :
Montreal Univ., Que., Canada
fYear :
1993
fDate :
19-22 Apr 1993
Firstpage :
230
Lastpage :
239
Abstract :
A new method to generate test patterns for multiple stuck-at faults in combinational circuits is presented. All multiple faults of any multiplicity are assumed present in the circuit and one does not have to resort to their explicit enumeration: the target fault is a single component of possibly several multiple faults. The authors try to generate test conditions that propagate the effect of the target fault to primary outputs regardless the effects of other faults which might be present in the circuit. When these conditions are fulfilled, the input vector is a test for the target fault and for all multiple faults containing the target fault as component. The method used a branch-and-bound technique and includes several heuristics to enhance the performance and fault detection. Experiments performed on the ISCAS´85 benchmark circuits show that high fault coverage can be obtained at a reasonable increase in cost
Keywords :
automatic testing; combinatorial circuits; fault location; integrated logic circuits; logic testing; ISCAS´85 benchmark circuits; branch-and-bound technique; combinational circuits; cost; fault coverage; fault detection; gate model; heuristics; input vector; line model; multiple faults; multiple stuck-at faults; target fault; test pattern generation; Benchmark testing; Circuit faults; Circuit simulation; Circuit testing; Combinational circuits; Costs; Electrical fault detection; Fault detection; Logic testing; Test pattern generators;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
European Test Conference, 1993. Proceedings of ETC 93., Third
Conference_Location :
Rotterdam
Print_ISBN :
0-8186-3360-3
Type :
conf
DOI :
10.1109/ETC.1993.246557
Filename :
246557
Link To Document :
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