Algebraic ATPG of combinational circuits using binary decision diagrams

The increasing size and complexity of VLSI circuits has brought testing and design for testability into the mainstream of the design process. However, VLSI designers have been reluctant to incorporate ATPG techniques into their environments because ATPG systems either take inordinate amounts of time in generating tests for faults or do not achieve significant fault coverage in the allotted time. Use of ordered binary decision diagrams (OBDDs) for function representation has provided significant impetus to algebraic CAD techniques. This paper presents techniques for gate-level ATPG using OBDDs. Such a system uses the path sensitization based TPG to generate tests for the easy faults and the OBDD based generator for the hard and redundant faults. The techniques presented can be generalized to arbitrary fault models