A new erase VT distribution model for reliability design in high density flash EEPROM

Author

Chi, Min-Hwa ; Haggag, Hosam ; Bergemont, Albert

Author_Institution

Fairchild Res. Center, Nat. Semicond. Corp., Santa Clara, CA, USA

fYear

1995

fDate

31 May-2 Jun 1995

Firstpage

326

Lastpage

330

Abstract

This paper describes an improved analytical F-N channel erase and V_T distribution model by including both process and cell parameters. This model is also able to predict the tightening of V_T distribution after using F-N soft reprogramming techniques. The accuracy of the model is verified by measured V_T curves and distribution. This new model provides a simple and useful tool for cell optimization and reliability design-in by accurately correlating V_TE distribution to physical parameters of process and memory cell

Keywords

EPROM; PLD programming; integrated circuit design; integrated circuit modelling; integrated circuit reliability; integrated memory circuits; F-N channel erase; F-N soft reprogramming techniques; cell optimization; cell parameters; erase VT distribution model; high density flash EEPROM; memory cell; process and cell parameters; reliability design; Capacitance; Design optimization; Doping; EPROM; Flash memory; Oxidation; Predictive models; Semiconductor device reliability; Semiconductor process modeling; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, Systems, and Applications, 1995. Proceedings of Technical Papers. 1995 International Symposium on

Conference_Location

Taipei

ISSN

1524-766X

Print_ISBN

0-7803-2773-X

Type

conf

DOI

10.1109/VTSA.1995.524713

Filename

524713