Emitter coupled logic testability analysis and comparison with CMOS & BiCMOS circuits

Author

Al-Khalili, D. ; Esonu, M.O. ; Rozon, C.

Author_Institution

Dept. of Electr. & Comput. Eng., R. Mil. Coll. of Canada, Kingston, Ont., Canada

fYear

1993

fDate

19-22 Apr 1993

Firstpage

263

Lastpage

272

Abstract

The logic behavior and performance of an ECL OR/NOR gate under a set of defect models are examined. These are compared with equivalent set of BiCMOS and CMOS gates. It is found that logical fault testing is inadequate for obtaining a sufficiently high fault coverage. Performance degradation faults such as delay, current and voltage transfer characteristics (VTC) or noise margin (NM) faults are analyzed as applied to these gates. It is shown that a combination of logical fault testing with delay fault testing yields the highest fault coverage for BiCMOS and CMOS gates. However, for an equivalent ECL gate, logical together with VTC fault testing methods promises a fault coverage of around 98%

Keywords

BiCMOS integrated circuits; CMOS integrated circuits; VLSI; emitter-coupled logic; fault location; integrated logic circuits; logic gates; logic testing; statistical analysis; BiCMOS; CMOS; ECL; OR/NOR gate; current faults; defect models; delay; fault coverage; fault testing; logic testability; noise margin; performance degradation; statistical analysis; voltage transfer characteristics; BiCMOS integrated circuits; CMOS logic circuits; Circuit faults; Circuit noise; Circuit testing; Coupling circuits; Degradation; Logic testing; Performance analysis; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

European Test Conference, 1993. Proceedings of ETC 93., Third

Conference_Location

Rotterdam

Print_ISBN

0-8186-3360-3

Type

conf

DOI

10.1109/ETC.1993.246562

Filename

246562