Title :
A multiple code-rate turbo decoder based on reciprocal dual trellis architecture
Author :
Lin, Chen-Yang ; Wong, Cheng-Chi ; Chang, Hsie-Chia
Author_Institution :
Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
fDate :
May 30 2010-June 2 2010
Abstract :
To increase channel efficiency for high throughput systems, the high code-rate schemes are usually required. However, conventional turbo decoders in high code-rate usually apply high radix trellis structure, and the complexity of the trellis increases exponentially according to the code-rate. In this paper, the reciprocal dual trellis is applied to reduce the trellis complexity and a multiple code-rate turbo decoder is proposed. A sign magnitude representation is also introduced to lower the hardware complexity. The puncturing methodology is applied to WCDMA system as a case study of high code-rate turbo codes, and the investigated code-rates are 1/3, 1/2, 2/3, and 4/5. The simulation results are also shown in this paper. Fabricated with CMOS 90nm process, the proposed decoder containing 370K logic gates and 58kb storage units can achieve 101Mb/s with 80mW at code-rate 4/5.
Keywords :
CMOS logic circuits; code division multiple access; communication complexity; logic gates; trellis codes; turbo codes; WCDMA system; channel efficiency; hardware complexity; high throughput systems; logic gates; multiple code-rate turbo decoder; radix trellis structure; reciprocal dual trellis architecture; sign magnitude representation; trellis complexity reduction; CMOS logic circuits; CMOS process; Computational modeling; Convolutional codes; Costs; Decoding; Hardware; Multiaccess communication; Throughput; Turbo codes;
Conference_Titel :
Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on
Conference_Location :
Paris
Print_ISBN :
978-1-4244-5308-5
Electronic_ISBN :
978-1-4244-5309-2
DOI :
10.1109/ISCAS.2010.5537361
