A deductive method for simulating transistor stuck-open faults in CMOS circuits

This paper presents a deductive method for simulating transistor stuck-open faults in CMOS circuits. A distinctive feature of the method is that it deduces all the detected transistor stuck-open faults by a robust test pattern using only one run of fault-free circuit simulation. No explicit simulation of faulty circuits is needed. The behavior of a good or faulty circuit is distinguished by whether or not a signal transition event applied to a primary input of the circuit can be properly propagated to one of the primary outputs. Experimental results are given for a number of benchmark circuits. It is shown that the simulator is capable of handling fairly large CMOS combinational circuits under robust test patterns