Effects of stress-induced mismatches on CMOS analog circuits

Author

Jaeger, Richard C. ; Ramani, Ramanathan ; Suling, J.C.

Author_Institution

Alabama Microelectron. Sci. & Technol. Center, Auburn Univ., AL, USA

fYear

1995

fDate

31 May-2 Jun 1995

Firstpage

354

Lastpage

360

Abstract

Degradation of element matching in CMOS analog circuits due to piezoresistive effects is discussed. The piezoresistive behavior of resistors is reviewed, and the response of CMOS devices to die stress is compared to the variation of resistors in CMOS technology. Theory and experimental results for stress induced changes in device parameters, matching in differential pairs and current mirrors and the offset voltage of CMOS op-amps are presented. General layout considerations for minimizing the response of CMOS analog circuits to die stress are discussed

Keywords

CMOS analogue integrated circuits; carrier mobility; integrated circuit layout; piezoresistance; CMOS analog circuits; current mirrors; die stress; differential pair matching; layout; offset voltage; op-amps; piezoresistive effects; stress-induced mismatches; Analog circuits; CMOS analog integrated circuits; CMOS technology; Degradation; Mirrors; Operational amplifiers; Piezoresistance; Resistors; Stress; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, Systems, and Applications, 1995. Proceedings of Technical Papers. 1995 International Symposium on

Conference_Location

Taipei

ISSN

1524-766X

Print_ISBN

0-7803-2773-X

Type

conf

DOI

10.1109/VTSA.1995.524719

Filename

524719