Title :
Overlap clocking technique for 10 bit 50 MHz 3 V D/A converter
Author :
Bhatt, Ansuya ; Singh, Raminder Jit ; Tan, Khen-Sang
Author_Institution :
Inst. of Microelectron., Nat. Univ. of Singapore, Singapore
fDate :
31 May-2 Jun 1995
Abstract :
A 10-bit high-speed Digital-to-Analog (D/A) converter with small silicon area has been designed and fabricated using a new technique of overlap clocking for current switching to achieve low glitch energy. Common centroid layout technique has been used to achieve 10 bit accuracy without using any trimming. The D/A converter achieves 30 pV.s glitch energy while operating at 50 MHz with 3 V supply
Keywords :
CMOS integrated circuits; digital-analogue conversion; timing; 10 bit; 3 V; 50 MHz; CMOS DAC; D/A converter; centroid layout technique; current switching; high-speed DAC; low glitch energy; overlap clocking; Circuit testing; Clocks; Driver circuits; Impedance; Low voltage; Microelectronics; Silicon; Switches; Switching circuits; Switching converters;
Conference_Titel :
VLSI Technology, Systems, and Applications, 1995. Proceedings of Technical Papers. 1995 International Symposium on
Conference_Location :
Taipei
Print_ISBN :
0-7803-2773-X
DOI :
10.1109/VTSA.1995.524720
