Case study of the pipelined arithmetic unit for the TI Advanced Scientific Computer

Introduction Many scientific applications today require computers which are very fast and capable of processing large amounts of data. Some advances in scientific processing have been slowed due to the lack of supercomputer capabilities which are required primarily in the area of Central Processor speed and the availability of large amounts of high speed memory. Particularly in the fields of modeling and simulation, additional speed and memory capacity are desired to allow increased resolution of the experiment. Technological developments in such things as integrated circuits, multilayer printed circuit boards, memory speeds, and others have contributed to the ability of computer manufacturers to serve this market. In addition to these developments, however, large advances had to be realized from the standpoint of the basic computer architecture. The concept of pipelining has provided an answer to the large data execution rate required. Pipelined capabilities in the form of arithmetic units and special purpose functional units are included in machines such as the CEC7600, IBM 360/195, CDC STAR-100, etc.^1,2 The Texas Instruments Advanced Scientific Computer (ASC) uses the pipeline concept throughout the Central Processor and carries the concept throughout the Central Processor and carries the concept further to include vector instructions in response to the high execution rates required.³