• DocumentCode
    3378478
  • Title

    High-speed zero-sum detection

  • Author

    Weinberger, Arnold

  • Author_Institution
    P.O. Box 390 International Business Machines Corporation Poughkeepsie, New York 12602
  • fYear
    1975
  • fDate
    19-20 Nov. 1975
  • Firstpage
    200
  • Lastpage
    207
  • Abstract
    A common requirement accompanying high-speed parallel addition is the early detection that the sum is equal to zero. Normally, this condition is detected from the sum, generally at least two logic gate levels after the sum.
  • Keywords
    Adders; Bismuth; Business; Delay; Equations; Logic gates;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer Arithmetic (ARITH), 1975 IEEE 3rd Symposium on
  • Conference_Location
    Dallas, TX, USA
  • Type

    conf

  • DOI
    10.1109/ARITH.1975.6157008
  • Filename
    6157008
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3378478